Different types of IC architectures are available with various characteristics, giving a designer a choice in selecting the most appropriate for a particular purpose, such as, for example, signal processing in communication systems.
ASICs have a number of advantages. ASICs typically operate at a relatively low power and, if a large production run is involved, can be inexpensive to manufacture. In addition, they can be more densely provided in a system because of their relatively lower power consumption, reducing cooling requirements. This is important as systems become increasingly complex and sophisticated, requiring increased processing capability. However, it is not possible to correct or update an existing ASIC. In case of errors, or if protocol standards are changed, an expensive and time-consuming respin is required, with field exchange of circuit packs. For equipment operating under well-established standards and protocols, a manufacturer may decide to use ASICs in a system, if an assessment demonstrates a low risk that subsequent changes may be needed to the design as originally configured. For the established SDH/SONET features in communications systems, this risk is manageable and ASICs are widely used.
One alternative to an ASIC is an FPGA. FPGAs offer enhanced versatility, as they may be re-configured after manufacture. However, they also have significant disadvantages compared to ASICs, being more expensive to manufacture and consuming significantly higher power. High power consumption may lead to potential full volume capacity being unattainable because sufficient cooling cannot be provided. As an example, a typical ASIC may cost $200 and consume 4 W whereas an equivalent FPGA may cost about $400 and consume 12 W of power. Network Processors (NPs) may be used as an alternative to FPGAs, but their costs and power consumption are typically greater than those of FPGAs.
In emerging technologies, or fields where standardization is not complete or subject to change, such as certain communication fields, a manufacturer may be exposed to a high risk of having to recall and re-install ASICs to accommodate changes subsequent to its equipment deployment. Thus, a manufacturer may be compelled to use the less satisfactory FPGA to achieve the required flexibility.
One proposal for harnessing the advantages of ASICs with the flexibility of FPGAs is to combine the two types in an IC architecture. The most stable part of an architecture is implemented by an ASIC and an embedded FPGA is included to allow adjustments to be made to less well-defined parts of the architecture as requirements change, or for those parts which might be subject to bugs and require later fixes. The FPGA may be re-configured following installation by downloading instructions when software is updated.
Another proposal for signal processing products used in an optical network involves providing a dedicated channel via which reconfiguration instructions are transmitted to an FPGA when reconfiguration is required. It is suggested that an overhead channel of the optical transport protocol “OTN” (Optical Transport Network) be used (see ITU-T G.709. Interfaces for the Optical Transport Network (OTN) and ITU-T G.789. Characteristics of the Optical Transport Network hierarchy equipment functional blocks). This approach can only be used for OTN systems and requires an OTN network and dedicated OTN connections to each system for the transport of the reconfiguration data. Other kinds of systems cannot be upgraded this way. Even if an OTN interface were be added to the systems, which would probably be impracticably expensive, an existing OTN network would be required to transport the reconfiguration data.
Similar concepts for transporting reconfiguration data using dedicated transport channels in an OTN system have been discussed in a master thesis by Mateusz Majer, “Evaluation of Reconfigurable Architectures for Overhead Processing in Optical Transport Networks”, Technical University of Darmstadt, 2003, and in a master thesis by Ashok-Kumar Chandra-Sekaran, “Reconfigurable RISC core based architecture for overhead processing in Optical Transport Network”, University of Karlsruhe, 2004.